by Staff Writers
Singapore (SPX) Dec 07, 2017
The current induced magnetisation switching by spin-orbit torque (SOT) is an important ingredient for modern non-volatile magnetic devices such as magnetic random access memories and logic devices that are required for high performance data storage and computing.
As such, researchers around the world are actively searching for novel ways to reduce the present high switching current density in order to achieve highly efficient SOT driven magnetisation switching. Researchers from the National University of Singapore (NUS) have recently made a significant breakthrough in this field of research.
Led by Associate Professor Yang Hyunsoo from the Department of Electrical and Computer Engineering, the NUS research team has, for the first time, successfully demonstrated room temperature magnetisation switching driven by giant SOTs in topological insulator/conventional ferromagnet (Bi2Se3/NiFe) heterostructures with an extremely low current density, that can address the issue of scalability and high power consumption needed in modern spintronic devices.
Assoc Prof Yang said, "Our findings can solve the fundamental obstacle of a high switching current in present heavy metal based SOT applications, and this is a big step towards room temperature topological insulator based spintronic device applications with ultralow power dissipation and high integration density. We believe our work will greatly invigorate topological insulator-based global research activities from diverse disciplines."
Employing novel quantum matter: topological insulators
"Due to spin-momentum-locked properties, as charge current flows in the TSS, all electron spins will be fully polarised in a perpendicular direction to the direction of the moving electron. Therefore, a very high efficient spin current generation and thus a giant SOT efficiency are expected in topological insulators." explained Dr Zhu Dapeng, who is a co-first author of the study and a Research Fellow at the Department.
Taking advantage of TSS is crucial to realise high performance topological insulator based SOT devices. However, in typical topological insulators such as Bi2Se3, the parasitic bulk states and two dimensional electron gas can contaminate and/or wash out the high SOT efficiency in TSS.
In order to overcome this, the research team has identified the TSS dominated SOT effect in ultrathin Bi2Se3 films (? 8 nm), exhibiting a large SOT efficiency up to 1.75 at room temperature, which is much larger than the values of ~0.01-0.3 in conventional used heavy metals.
High performance topological insulator based devices for data storage and computing
The team demonstrated the high efficient current induced magnetisation switching at room temperature using topological insulator Bi2Se3 (8 nm), which can be grown in a wafer scale using molecular beam epitaxy (MBE), with a conventional 3D ferromagnet NiFe (6 nm), which is widely utilised in various industries.
"Our work successfully presents a significant reduction of switching current density for the magnetisation switching by utilising the giant SOT effect in Bi2Se3. The value is about 6+ 105 A/cm2, which is almost two orders of magnitude smaller than that of heavy metals.
This is a major milestone for the ultralow power consumption and high integration density SOT device applications. Moreover, our devices work robustly at room temperature, which breakouts the limit of ultralow working temperature in previous TI device." said Dr Wang Yi of the Department, who is the other co-first author of the study.
"Our magnetisation switching scheme does not require an assistive magnetic field. This makes the topological insulator/ferromagnet material systems easy to integrate into the well-established industrial technology for magnetic devices," added Assoc Prof Yang.
The finding of the study was published in the scientific journal Nature Communications on 8 November 2017.
Washington DC (SPX) Nov 30, 2017
Researchers at the National Institute of Standards and Technology (NIST) have invented a new approach to testing multilayered, three-dimensional computer chips that are now appearing in some of the latest consumer devices. The new method may be the answer the semiconductor industry needs to quickly assess the reliability of this relatively new chip construction model, which stacks layers of flat ... read more
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