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TRW and Fujitsu Complete Flight Production of Extremely High-Density Chips For Astrolink Payload

The Application Specific Integrated Circuits (ASICs), the key technology for Astrolink's on-board processing, were designed by TRW and fabricated by Fujitsu in just 19 months. The largest ASIC features 5.5 million gates - the equivalent of 18 million transistors, providing more processing power than Pentium III chips.
Redondo Beach - May 15, 2001
Flight production of extremely high-density digital integrated circuits for the TRW-built Astrolink communications payload is now complete, demonstrating rapid progress in meeting key hardware milestones.

Astrolink International LLC is a global broadband communications system. TRW is building the communications payload for Lockheed Martin Commercial Space Systems, the prime contractor for the Astrolink Space segment.

The Application Specific Integrated Circuits (ASICs), the key technology for Astrolink's on-board processing, were designed by TRW and fabricated by Fujitsu in just 19 months. The largest ASIC features 5.5 million gates - the equivalent of 18 million transistors, providing more processing power than Pentium III chips.

"These ASIC chips represent a tremendous technical achievement," said Mike McVey, TRW Astrolink Payload program manager. "They have greater data handling capacity and offer dramatic savings in size, weight and power consumption, making them ideally suited for broadband applications. And development sped along at one-third the time normally required."

"Astrolink is the industry's most exciting space-based broadband system, and the TRW-built payload takes advantage of the very latest ASIC technology," said Keith Horn, marketing director for Fujitsu Microelectronics, Inc., which fabricated the chips for TRW.

"We at Fujitsu are very pleased with the results of our development program and will continue to work with TRW to meet their hardware objectives."

Extensive system modeling was performed on the ASICs prior to committing the designs to fabrication. This enabled 100 percent first-pass success. Exhaustive functional testing of the engineering model Astrolink payload, including the fully functional on-board processor, is underway at TRW.

The Astrolink processor is comprised of a bank of digital demodulators and an ATM router.

  • Each demodulator ASIC contains the processing required to flexibly channelize, demodulate, decode and synchronize all 175 broadband channels within a beam, the system equivalent of a cable modem or DSL hub. To accomplish this, the channelizer/demodulator ASIC is composed of 5.5 million gates and performs 34 giga-operations per second.

  • The ATM router is comprised of eight ASIC designs, ranging between 100,000 and four million gates. These ASICs will perform data processing functions, such as switching, routing and flow control.

Related Links
Astrolink
TRW
Fujitsu Microelectronics
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TECH SPACE
64-BIT Risc Processor Set To Enter Space Service
Tokyo - March 12, 2001
MIPS Technologies, Inc. said Monday that the first 64-bit RISC microprocessor chip for space applications has been developed by High-Reliability Components Corporation (HIREC) of Tokyo, under contract to the National Space Development Agency of Japan.



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