The microprocessor chip is based on MIPS Technologies' leading 64-bit processor architecture for high-performance, low-power embedded applications.

Development of the microprocessor chip was a collaborative effort, led by HIREC, among leading technology providers. Toshiba Corporation, a licensee of the MIPS architecture, developed the 64-bit TX49 processor core intellectual property. NEC Corporation developed the chip's large-scale gate-array technology, and Kyocera Corporation developed highly reliable packaging suitable for use in space.

NASDA plans to use the chip in satellite applications, beginning with the Engineering Test Satellite VIII, which will establish and verify the world's largest geostationary satellite bus technology and the Advanced Land Observing Satellite, which will be used for cartography, regional observation, disaster monitoring and resource surveying.

"Space applications are among the most demanding of all; performance, power, and stability all are paramount. We are, of course, delighted that HIREC demonstrated their confidence in the MIPS architecture and chose our licensee Toshiba for this critical application," said John Bourgoin, chairman and CEO of MIPS Technologies.

"Toshiba and MIPS Technologies have a 10-year history of collaboration in the development of 32- and 64-bit high-performance processor solutions in a variety of embedded applications, including the digital consumer and automotive markets."

"The use of MIPS-based technology in the TX49 core, incorporated into a rigorous space-based project, underscores the broad applications of the MIPS architecture and the TX49," said Masahiko Ono, technology executive of the Semiconductor Company for Toshiba Corporation. "We expect that the core nurtured through our joint development efforts has applications for other markets."

The features implemented by Toshiba to handle the rigors of space and ensure reliable operation include:

• MIPS instruction set
• 36-bit address bus (64-bit virtual address), 64-bit data bus
• 8KB instruction cache, 8KB data cache with 8-bit error detection & correction
• 25MHz pipeline frequency
• 50MHz external clock (a selectable feature for the bus clock rate)
• 64-bit general-purpose registers, integer unit, floating point registers, and floating point unit
• Operating voltage of 3.3V (5.0V I/O tolerance)
• Operating temperature of -40 to +85 degrees C
• 304-pin ceramic flat package

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